The present invention relates to the manufacturing of semiconductor devices, and more particularly, to low-k interlevel and intermetal dielectrics in semiconductor devices.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micron-sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the sub-micron-features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, usually of doped monocrystalline silicon (Si), and a plurality of sequentially formed inter-metal dielectric layers and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of vertically spaced metallization levels are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the inter-metal dielectric layer separating the metallization levels, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and microminiaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization levels is known as xe2x80x9cdamascenexe2x80x9d -type processing. Generally, this process involves forming a via opening in the inter-metal dielectric layer or interlayer dielectric (ILD) between vertically spaced metallization levels which is subsequently filled with metal to form a via electrically connecting the vertically spaced apart metal features. The via opening is typically formed using conventional lithographic and etching techniques. After the via opening is formed, the via is filled with a conductive material, such as tungsten (W), using conventional techniques, and the excess conductive material on the surface of the inter-metal dielectric layer is then typically removed by chemical mechanical planarization (CMP).
A variant of the above-described process, termed xe2x80x9cdual damascenexe2x80x9d processing, involves the formation of an opening having a lower contact or via opening section which communicates with an upper trench section. The opening is then filled with a conductive material to simultaneously form a contact or via in contact with a conductive line. Excess conductive material on the surface of the inter-metal dielectric layer is then removed by CMP. An advantage of the dual damascene process is that contact or via and the upper line are formed simultaneously.
High performance microprocessor applications require rapid speed of semiconductor circuitry, and the integrated circuit speed varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the sub-micron range, step coverage problems result from the use of Al. Poor step coverage causes high current density and enhanced electromigration. Moreover, low dielectric constant polyamide materials, when employed as inter-metal dielectric layers, create moisture/bias reliability problems when in contact with Al, and these problems have decreased the reliability of interconnections formed between various metallization levels.
One approach to improved interconnection paths in vias involves the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for the metallization level and W plugs for interconnections between the different metallization levels. The use of W, however, is attendant with several disadvantages. For example, most W processes are complex and expensive. Furthermore, W has a high resistivity, which decreases circuit speed. Moreover, Joule heating may enhance electromigration of adjacent Al wiring. Still a further problem is that W plugs are susceptible to void formation, and the interface with the metallization level usually results in high contact resistance.
Another attempted solution for the Al plug interconnect problem involves depositing Al using chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures. The use of CVD for depositing Al is expensive, and hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI semiconductor devices, which require multi-level metallization levels. Cu and Cu-based alloy metallization systems have very low resistivities, which are significantly lower than W and even lower than those of previously preferred systems utilizing Al and its alloys. Additionally, Cu has a higher resistance to electromigration. Furthermore, Cu and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver (Ag) and gold (Au). Also, in contrast to Al and refractory-type metals (e.g., titanium (Ti), tantalum (Ta) and W), Cu and its alloys can be readily deposited at low temperatures formed by well-known xe2x80x9cwetxe2x80x9d plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of manufacturing throughput.
Electroless plating of Cu generally involves the controlled auto-catalytic deposition of a continuous film of Cu or an alloy thereof on a catalytic surface by the interaction of at least a Cu-containing salt and a chemical reducing agent contained in a suitable solution, whereas electroplating comprises employing electrons supplied to an electrode (comprising the surface(s) to be plated) from an external source (i.e., a power supply) for reducing Cu ions in solution and depositing reduced Cu metal atoms on the plating surface(s). In either case, a nucleation/seed layer is required for catalysis and/or deposition on the types of substrates contemplated herein. Finally, while electroplating requires a continuous nucleation/seed layer, very thin and discontinuous islands of a catalytic metal may be employed with electroless plating.
Another technique to increase the circuit speed is to reduce the capacitance of the inter-metal dielectric layers. Dielectric materials such as silicon oxide (SiO2) have been commonly used to electrically separate and isolate or insulate conductive elements of the integrated circuit from one another. However, as the spacing between these conductive elements in the integrated circuit structure has become smaller, the capacitance between such conductive elements because of the dielectric being formed from silicon oxide is more of a concern. This capacitance negatively affects the overall performance of the integrated circuit because of increased power consumption, reduced speed of the circuitry, and cross-coupling between adjacent conductive elements.
In response to the problem of capacitance between adjacent conductive elements caused by use of silicon oxide dielectrics, other dielectric materials, commonly known as low-k dielectrics, have been used. Whereas silicon oxide has a dielectric constant of approximately 4.0, many low-k dielectrics have dielectric constants less than 3.5. Examples of low-k dielectric materials include organic or polymeric materials. Another example is porous, low density materials in which a significant fraction of the bulk volume contains air, which has a dielectric constant of approximately 1. The properties of these porous materials are proportional to their porosity. For example, at a porosity of about 80%, the dielectric constant of a porous silica film, i.e. porous SiO2, is approximately 1.5. Still another example of a low-k dielectric material is carbon doped silicon oxide wherein at least a portion of the oxygen atoms bonded to the silicon atoms are replaced by one or more organic groups such as, for example, an alkyl group such as a methyl (CH3xe2x80x94) group.
A problem associated with the use of many low-k dielectric materials is that resist material can diffluse into the low-k dielectric material, and the low-k material can be damaged by exposure to oxidizing or xe2x80x9cashingxe2x80x9d systems, which remove a resist mask used to form openings, such as vias, in the low-k dielectric material. These processes can damage the low-k dielectric material by causing the formation of hydroxyl (OH) terminated species at exposed surfaces of the low-k dielectric material. Hydroxyl ions are polar, and these polar groups tend to attract water, which is a bipolar molecule. Thus, the damaged surface of the low-k dielectric material becomes hygroscopic. Subsequent processing, such as annealing, can result in water vapor formation, and absorption of water by the low-k dielectric material can cause an undesirable increase in the dielectric constant of the low-k dielectric material. For this reason in particular, the upper surface of the low-k dielectric material is typically protected by a capping layer, such as silicon oxide, disposed over the upper surface.
A number of different variations of a damascene process using low-k dielectrics have been employed during semiconductor manufacturing. With reference to FIGS. 1A-1G, an example of a damascene process for forming vias between vertically spaced metallization levels, according to conventional techniques, will be described. This process can be repeated to form multiple metallization levels, i.e., two or more, stacked one on top of another.
In FIG. 1A, a first barrier layer 12 is deposited over a first metallization level 10. The first barrier layer 12 acts as a passivation layer that protects the first metallization level 10 from oxidation and contamination and prevents the material of the metallization level 10 from diffusing into a subsequently formed dielectric layer. The first barrier layer 12 also acts as an etch stop during subsequent etching of the dielectric layer. A typical material used as an etch stop is silicon nitride, and approximately 500 angstroms of silicon nitride is typically deposited over the metallization level 10 to form the first barrier layer 12. An illustrative process used for depositing silicon nitride is plasma enhanced CVD (PECVD).
In FIG. 1B, a first low-k dielectric layer 14 is deposited over the first barrier layer 12. The majority of low-k dielectric materials used for a dielectric layer are based on organic or inorganic polymers. The liquid dielectric material is typically spun onto the surface under ambient conditions to a desired depth. This is typically followed by a heat treatment to evaporate solvents present within the liquid dielectric material and to cure the film to form the first low-k dielectric layer 14.
After formation of the first low-k dielectric layer 14, a capping layer 13 is typically formed over the first low-k dielectric layer 14. The function of the capping layer 13 is to protect the first low-k dielectric layer 14 from the process that removes a subsequently formed resist layer. The capping layer 13 is also used as a mechanical polishing stop to prevent damage to the first low-k dielectric layer 14 during subsequent polishing away of conductive material that is deposited over the first low-k dielectric layer 14 and in a subsequently formed via. Examples of materials used as a capping layer 13 include a silicon oxide and silicon nitride.
In FIG. 1C, vias 16 are formed in the first low-k dielectric layer 14 using conventional lithographic and etch techniques. The lithographic process involves depositing a resist 17 over the capping layer 13 and exposing and developing the resist 17 to form the desired patterns of the vias 16. The first etch, which is highly selective to the material of the first low-k dielectric layer 14 and the capping layer 13, removes the capping layer 13 and the first low-k dielectric layer 14 until the etchant reaches the first barrier layer 12. The first etch is typically an anisotropic etch, such as a reactive ion plasma dry etch, that removes only the exposed portions of the first low-k dielectric layer 14 directly below the opening in the resist 17. By using an anisotropic etch, the via 16 can be formed with substantially perpendicular sidewalls.
In FIG. 1D, the resist 17 is removed from over the first dielectric layer 14. A typical method of removing the resist 17 is known as xe2x80x9cashingxe2x80x9d whereby the resist 17 is oxidized with an O2 plasma at elevated temperatures. After the resist 17 is removed, a second etch, which is highly selective to the material of the first barrier layer 12, removes the first barrier layer 12 until the etchant reaches the first metallization level 10. The second etch is also typically an anisotropic etch.
In FIG. 1E, an adhesion/barrier material, such as tantalum, titanium, tungsten, tantalum nitride, or titanium nitride, is deposited. The combination of the adhesion and barrier material is collectively referred to as a second barrier layer 20. The second barrier layer 20 acts to prevent diffusion into the first low-k dielectric layer 14 of the conductive material subsequently deposited into the via 16.
In FIG. 1F, a layer 22 of a conductive material, for example, a Cu or Cu-based alloy, is deposited into the via 16 and over the dielectric layer 14. A typical process initially involves depositing a xe2x80x9cseedxe2x80x9d layer on the second barrier layer 20 subsequently followed by conventional plating techniques, e.g., electroless or electroplating techniques, to fill the via 16. So as to ensure complete filling of the via 16, the Cu-containing conductive layer 22 is deposited as a blanket (or xe2x80x9coverburdenxe2x80x9d) layer 24 so as to overfill the via 16 and cover the upper surface 26 of the capping layer 13.
In FIG. 1G, the entire excess thickness of the metal overburden layer 24 over the upper surface 26 of the capping layer 13 is removed using a CMP process. A typical CMP process utilizes an alumina (Al2 O3)-based slurry and leaves a conductive plug in the via 16. The conductive plug has an exposed upper surface 30, which is substantially co-planar with the surface 26 of the capping layer 13.
Although a capping layer is typically used to protect the low-k dielectric from the ashing process and the CMP process, the formation of the capping layer itself can disadvantageously damage the low-k dielectric. Accordingly, a need exists for an improved method of forming low-k dielectric layers that provides protection to the low-k dielectric from subsequent processing, such as during the formation of the capping layer.
This and other needs are met by embodiments of the present invention which provide a method of manufacturing a semiconductor device. The method includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer, doping a first portion of the dielectric layer, forming a capping layer over the dielectric layer, forming an opening through the dielectric layer, and filling the opening with metal to form a first metal feature. The first portion can formed by doping with hydrogen using ion implantation or plasma etching. Doping the first portion can also roughen a top surface of the first dielectric layer.
By providing a dielectric layer having a doped first portion, the first portion can protect the dielectric layer from the process that forms that capping layer. The process of forming the first portion can also roughen the top surface of the first dielectric layer, which promotes better adhesion of the first dielectric layer to the subsequently formed capping layer.
In an aspect of the invention, the dielectric layer has a dielectric constant less than about 3.5. Also, the metal and the first level can comprise copper (Cu) or a Cu alloy. Furthermore, the opening can be a via opening, a trench, or a dual damascene opening comprising a lower via opening in communication with an upper trench; and the first metal feature can comprise a via, a line, or a combination of a lower via in contact with an upper line, respectively. The thickness of the first portion can be at least 100 angstroms after the doping step. Also, if the dielectric layer is formed from a low-k material, the doping of the first portion densities the low-k material.
In an additional embodiment of the present invention, a semiconductor device comprises a first level, a first barrier layer, a dielectric layer having a first portion and a second portion, a capping layer, an opening in the dielectric layer, and metal within the opening. The first barrier layer is disposed over the first level, and the dielectric layer is disposed over the first barrier layer. The opening extends through the first dielectric layer and the first barrier layer to the first level. The first portion has a higher hydrogen content than the second portion of the dielectric layer. Furthermore, the first dielectric layer can include a roughened top surface.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.